Analog IC Layout Engineer – FinFET Technologies

ADVANS Group in Portugal is looking for experienced Analoc IC Layout Engineers to work in the semiconductor industry in our new Lisbon offices.

Key Responsibilities:

• Design and implement analog IC layouts including floor planning, integration, area estimation, and abstract view generation
• Perform placement and routing at block, top, and full-chip levels in the Cadence Virtuoso environment
• Develop and layout I/O structures, ESD protection, PADs, and seal rings following advanced node constraints
• Execute and debug physical verification checks including DRC, LVS, ERC, and antenna rule checks using industry-standard tools (Assura, PVS, Calibre)
• Conduct parasitic and electromigration (EM) extractions, and collaborate closely with Analog Design Engineers to ensure performance and reliability
• Address and optimize FinFET-specific challenges, including layout-dependent effects (LDE), double-patterning, DFM, and reliability constraints in nodes below 10nm

Qualification Requirements:

• BSc or MSc in in electrical engineering or related field
• 5+ years of professional experience in Analog IC Layout, with at least 2 years in FinFET technologies (e.g., 7nm, 5nm, 3nm nodes)
• Hands-on experience with Cadence Virtuoso, Assura, PVS, and/or Mentor Calibre layout and verification tools
• Strong understanding of analog layout principles, ESD/LU protection, parasitic-aware design, DFM, EM, antenna effects, and FinFET-specific LDE
• Comfortable working in a Linux-based CAD environment
• Scripting knowledge (e.g., SKILL, Shell, Perl, TCL) is a plus
• Excellent English communication skills, both written and verbal

Benefits:

• Integration program in a professional, young & dynamic team
• Professional development opportunities
• Competitive salaries & benefits
• Health insurance
• International work environment