Senior PLL and Clock Distribution Expert (startup)

Senior IC Design Engineer

San Diego, CA (onsite/hybrid)

US Citizen or US Permanent Resident (preferred)

Full-Time + Health Benefits + 401K Plan + PTO + Founder Shares

Requirements:

High-speed time-interleaved ADCs (SAR, pipeline, TDC, etc.), RF front-end design, SerDes, miscellaneous functions (other data converters, filters, amplifiers, PLLs, power management, oscillators, etc.) in FinFET technologies.

MS with 5+ years or PhD with 3+ years of experience preferred.

Strong PLL and clock distribution experience is preferred