Machine Learning Engineer (ML for Chip Design)

Responsibilities

• Train, fine-tune, and post-train large language models for chip design and verification tasks using supervised fine-tuning, human-feedback training, and reinforcement learning.
• Build and maintain data pipelines, including data collection, cleaning, and synthetic data creation.
• Design strong evaluation methods to measure model accuracy and AI agent performance.
• Work with research scientists, systems engineers, and chip-design experts to turn research ideas into production AI agents.
• Use large GPU clusters to run experiments, study model behavior, and improve AI code-generation workflows.

Requirements

• B.S., M.S., or PhD in Computer Science, Electrical Engineering, or a related field.
• Alternatively, 2–10 years as an ML engineer, or a recent PhD graduate.
• Hands-on experience training or fine-tuning LLMs using Python and PyTorch.
• Familiarity with distributed GPU training and inference (vLLM, SGLang, CUDA, Ray).
• Able to work on-site 5 days a week in San Jose.

Skills Required

• LLM fine-tuning (SFT, RLHF) & post-training
• Python & PyTorch
• Hugging Face Transformers
• Distributed GPU training/inference (vLLM, SGLang, CUDA, Ray)
• Data pipelines & synthetic data
• Model evaluation frameworks
• Agentic AI workflows
• Hardware design languages (RTL, Verilog, SystemVerilog), an advantage