Staff/Senior Device Technology Device Engineer (Layout)

Job brief

• Develop, maintain, and optimize complex PCells to support large-scale and highly parameterized layout generation.

• Device tape out preparation and FDK coordination.

• Device test structure data collection, analysis

Requirement

• Degree (or above) preferred in physics, EE.

• Hands-on experience with Laker or Cadence Virtuoso for custom layout design.
• Strong programming skills, with experience in at least one of the following (or similar) for layout automation and PCell development: C/C++ or other scripting languages used in EDA environments.
• Proven ability to develop and debug complex PCells and support batch generation of layouts.
• Solid understanding of CMOS processes, device structures, and layout design rules
• Working Experience: hands on experience on layout work.

Interested applicants please send your resume to Kyle.hui@gmprecruit.com for express processing.


Thank you.

GMP Technologies (S) Pte. Ltd. | EA License: 11C3793
Kyle Hui | EA Personnel Registration: R1333144