Senior ASIC Hardware Engineer - Physical Implementation & Sign-Off

️ Senior ASIC Hardware Engineer Physical Implementation & Sign-Off

Zürich | Deep Tech | SoC / ASIC |
Hybrid | Full-time | High-impact role

We are supporting a cutting-edge technology company in Zürich that is seeking a motivated Senior ASIC Hardware Engineer who can take ownership of advanced physical design challenges either from a Timing Closure angle or a Power Integrity / IR-Drop perspective. This is a full-time permanently employed position.

If you enjoy solving deep chip-level problems, working on advanced nodes, and collaborating closely with world-class design teams, this one is for you.

What this role is about

You will play a key role in the sign-off of complex IP and SoC blocks, working with both digital backend and full-custom teams. Depending on your strengths, you could focus more on:

️ Timing Closure & STA

or

Power Integrity, IR Drop & EM

Both skill sets are equally welcome the company will adapt the role to the strengths of the right engineer.

What you will be doing

Your responsibilities will vary depending on whether your expertise leans toward Timing or Power Integrity, but may include:

️ If your strength is Timing Closure:

• Building, refining & maintaining timing constraints (clocks, I/O timing, exceptions)
• Running STA across corners/modes & landing reliable setup/hold closure
• Collaborating with synthesis, P&R & clock-tree teams to guide design decisions
• Debugging skew/jitter issues & improving clocking strategy
• Leading functional & timing ECO loops to convergence
• Supporting GLS, SDF, and verification teams with timing data

If your strength is IR / Power Integrity:

• Planning & reviewing power grids (straps, taps, decaps, via strategy)
• Running IR drop & EM analysis throughout the flow (early + post-route)
• Identifying hot spots and driving actionable fixes
• Working with RTL, layout, and timing teams to improve robustness
• Generating SAIF/VCD activity & validating realistic workloads
• Enhancing power-analysis flows with automation & reproducible scenarios

For both profiles:

• Collaborating closely with custom-design, digital, backend & verification teams
• Ensuring smooth integration of custom macros into digital flows
• Writing clear documentation, guidelines & reusable collateral
• Improving automation using Python or Tcl
• Contributing to first-time-right tapeouts on modern technology nodes

Who will thrive in this role

You don't need to be an expert in both timing and IR drop but you must be strong in at least one.
Here is what they are looking for:

• 5+ years of experience in ASIC backend / physical design
• Hands-on exposure to STA, P&R, CTS, ECO loops, or IR-drop/EM analysis
• Experience working from synthesis route sign-off
• Understanding of how physical choices impact timing, power & reliability
• Ability to interpret reports and quickly turn them into practical fixes
• Experience on advanced nodes (sub-14nm) is a plus
• Confident scripting in Tcl or Python
• A collaborative mindset & clear documentation habits

Experience with power-gated designs, multi-voltage flows, thermal considerations, scan/MBIST, or large hierarchical SoC closure is advantageous.

Backgrounds that fit well

Candidates coming from:

• Semiconductor companies
• SoC design houses
• Accelerator / AI hardware companies
• Physical design consultancies
• Memory or custom-silicon teams

tend to do extremely well in this role.

Location & Setup

Based in Zürich
Hybrid working model (onsite collaboration with flexibility)