Senior Digital Hardware Engineer (RTL & Verification) Zurich | Hybrid

Senior Digital Hardware Engineer (RTL & Verification) Zurich | Hybrid

We are supporting one of our Swiss technology partners in their search for a Senior Digital Hardware Engineer to strengthen their growing silicon team in Zürich.

This is a permanent role, is ideal for someone who enjoys owning IP blocks end-to-end, thrives in cross-functional environments, and wants to contribute to next-generation compute architectures.

🔍 What youll be doing

In this position, you will play a central role in the creation and validation of complex digital IPs used within an advanced compute platform. Your work will cover both RTL development and verification, including:

Designing digital components in SystemVerilog RTL that are fully synthesizable and robust.

Building and maintaining verification environments (UVM-based) to ensure functional maturity before tape-out.

Implementing control, interface and data-movement logic such as bus/register interfaces, DMA behaviour, bridges, FIFOs, arbiters, etc.

Working closely with analog/custom design teams, physical design, and embedded software engineers to ensure alignment on performance, timing and integration.

Contributing to test strategies: directed + constrained-random testing, coverage tracking, and debugging.

Supporting later project phases such as FPGA validation or gate-level simulations when needed.

Creating clear design documentation, specifications, and reusable verification components.

🎯 What success looks like

Digital IPs delivered with high-quality RTL, clean sign-off (lint/CDC), and complete functional/code coverage.

Verification environments that are reliable, automated, reusable, and effective at catching corner cases.

Smooth integration with internal teams and predictable design milestones.

Strong contribution to a platform pushing the boundaries of low-power compute architectures.

🧩 What were looking for

5+ years in digital design or design verification for ASIC/SoC projects.

Solid hands-on SystemVerilog RTL experience (verification knowledge also valuable).

Familiarity with ARM or RISC-Vbased systems, either from integration or design work.

Understanding of synthesis concepts and how design choices influence power, timing, and area.

Ability to write clean, structured, well-documented code and communicate clearly in a technical team.

Bonus skills (not required)

Experience around memory-related IP (SRAM controllers, power-aware flows, scan/DFT).

Familiarity with AMBA protocols and common digital building blocks (FIFOs, arbiters, resets, CDC schemes).

Gate-level simulation experience, FPGA prototyping exposure.

Python or Tcl scripting for automation, regression or debugging.

Background in AI/DSP acceleration or dataflow architectures.

📍 Location & Setup

Zürich, Switzerland

Permanent full-time

Hybrid working setup (office + some home office flexibility)