Job Openings (Mid/Sr/Princ) Verification Design Engineer (UVM/Infrastructure)

About the job (Mid/Sr/Princ) Verification Design Engineer (UVM/Infrastructure)

In this role, you will be driving key aspects of our AI/ML SoC and custom accelerators verification and emulation. You will drive the definition and development of verification flows and processes, pre-silicon verification and post-silicon test generation

You would have organizational leadership experience in supporting high-performance teams and processes, be a strategic problem-solver with demonstrated collaboration and communication skills.

Responsibilities:

  • Responsible for all aspects of verification and regression flows.
  • Development of Verification infrastructure. Be instrumental is setting up EDA flows and processes to improve verification productivity and regression including tools to submit and manage large-scale regressions.
  • Definition and development of UVM testbench infrastructure.
  • Development of coverage plans including code coverage, functional coverage. Build verification test benches to enable block/SoC/system level verification.
  • Emulation flow development.

Requirements:

  • Natural leader who enjoys working with hardware and software development teams
  • Excellent organization skills to prioritize requirements.
  • Experience in pre-silicon verification of CPU, GPU, AI/ML or any complex SoC development highly desirable.
  • Hands-on experience with System Verilog and UVM, prefer experience with High-Level Synthesis and System C.
  • Hands-on experience in the development of verification plans and infrastructure.
  • Hands-on experience in test writing with ARM AXI, APB protocols and on-chip NOC
  • Experience in Python and scripting.
  • Team player that proactively engages with cross-functional engineering teams.
  • Experience working with and directing external contractors.
  • Working knowledge of Git, Jenkins, Gerrit is a definite plus.
  • BSEE +4 years of relevant design verification experience